Memory cell and method of manufacturing

Storage cell comprises a storage layer structure arranged between a semiconductor body (1) and a gate electrode (5,6); a source line as a common source connection for several storage cells and a source region (S) between the gate electrode and a further gate electrode; and a drain line formed as a metallic conducting pathway electrically connected to a drain region (D). The storage layer structure consists of a storage layer between a first limiting layer and a second limiting layer. The gate electrode is part of the gate line and formed as a strip. The drain line runs across the gate line and is arranged as a bit line isolated from the gate line. An Independent claim is also included for a process for the production of a storage cell arrangement. Preferred Features: A polysilicon layer (17) is formed above both the drain region and the source region. The storage layer is made of silicon nitride and the limiting layers are made of silicon oxide, or the storage layer is made of tantalum oxide and the limiting layers are made of silicon oxide, or the storage layer is made of silicon hafnium oxide or hafnium silicate or zirconium oxide or zirconium silicate and the limiting layers are made of aluminum oxide or aluminum-containing silicon oxide.