Sub-pipelined and pipelined execution in a VLIW achitecture

A subpipelined translation embodiment providing binary compatibility between current and future generations of DSPs is disclosed. When a fetch packet is retrieved from memory(INSTRUCTION MEMORY), the entire fetch packet is assigned an operating mode (base instruction set or migrant instruction set) according to the execution mode (EXECUTION MODE) at the time the request was made to the instruction memory for the fetch packet. The fetch packets from the instruction memory are parsed into execute packets and sorted by execution unit (dispatched) in a datapath (SHARED DATAPATH) shared by both execution modes (base and migrant). Because the fetch packet syntax and execution unit encoding is different between the migrant and base architecture in this case, the two execution modes have separate control logic (BASE ARCHITECTURE CONTROL, MIGRANT ARCHITECTURE CONTROL). Instructions from the dispatch datapath are decoded by either base architecture decode logic or the migrant architecture decode logic, depending on the execution mode bound to the parent fetch packet of the instructions being decoded. Code processed by the migrant and base decode pipelines produces machine words (MACHINE WORD) that control the register files and the execution hardware functional units. These machine words are selected with a multiplexer. The choice of the eventual machine word from the multiplexer is governed by the operating mode bound to the fetch packet that produced the machine word and sequencing logic for sub-pipelined execution (SUBPIPELINE CONTROL). The selected machine word controls a global register file, which supplies operands to all hardware execution units and accepts results of all hardware execution units.