Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication

A process is provided for planarization of an insulation layer (122), e.g., of silicon dioxide, on a semiconductor wafer (121), e.g., of silicon, and having a surface with a downwardly stepped chemically mechanically polished arrangement of metal lines (126) in the insulation layer between intervening insulation portions (182). A first pattern portion (PF1) of metal lines is separated by intervening insulation portions and defines a first pattern factor having a first value, and an adjacent second pattern portion (PF2) of metal lines is separated by intervening insulation portions and defines a second pattern factor having a second value different from the first value. The second pattern portion (PF2) is at a step depth relative to the insulation layer surface (182) different from that of the first pattern portion relative (PF1) to such layer surface. The process involves chemically mechanically polishing the insulation layer surface (182) and first and second pattern portions (PF1, PF2) to reduce the step depths of the pattern portions relative to the insulation layer surface (182) and to each other, for planarizing the insulation layer surface and pattern portions relative to each other. The process further involves providing a further insulation layer on the planarized insulation layer, and a further arrangement of metal lines in the further insulation layer, and chemically mechanically polishing the further arrangement of metal lines.