COMPLEMENTARY BIPOLAR/CMOS EPITAXIAL STRUCTURE AND PROCESS

An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850 DEG C. As the substrate is heated to a temperature of 1050 DEG C. N+ dopant gas is injected into the carrier gas to suppress autodoping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080 DEG C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080 DEG C. Then an N- epitaxial layer is deposited on the second cap layer at 1080 DEG C. The harmful effects of a dip in the dopant concentration profile at the bottoms of the collectors of the NPN transistors are avoided by the process.