PROCESS AND MANUFACTURING TOOL ARCHITECTURE FOR USE IN THE MANUFACTURE OF ONE OR MORE METALLIZATION LEVELS ON A WORKPIECE

A semiconductor manufacturing tool configuration and corresponding process for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a semiconductor workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed.

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Bibliographische Detailangaben
Hauptverfasser:	STEVENS, E., HENRY, BERNER, ROBERT, W
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRIC ELEMENTS BEER BIOCHEMISTRY CHEMISTRY COMPOSITIONS THEREOF CULTURE MEDIA ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ENZYMOLOGY METALLURGY MICROBIOLOGY MICROORGANISMS OR ENZYMES MUTATION OR GENETIC ENGINEERING PROPAGATING, PRESERVING OR MAINTAINING MICROORGANISMS SEMICONDUCTOR DEVICES SPIRITS VINEGAR WINE
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Beschreibung
Zusammenfassung:	A semiconductor manufacturing tool configuration and corresponding process for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a semiconductor workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed.