Method and apparatus for generating test pattern for circuit blocks

In a method for generating a test pattern for testing at least one circuit block (24-1, 24-2, 24-3) of a semiconductor device including a control circuit (21) connected to the circuit block the above-mentioned test pattern is generated by converting a common test pattern (11) for the circuit block w...

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Bibliographische Detailangaben
1. Verfasser:	OTSUKA, SHIGEKAZU
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES STATIC STORES TESTING
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Zusammenfassung:	In a method for generating a test pattern for testing at least one circuit block (24-1, 24-2, 24-3) of a semiconductor device including a control circuit (21) connected to the circuit block the above-mentioned test pattern is generated by converting a common test pattern (11) for the circuit block with reference to a data conversion library (12) corresponding to characteristics of the control circuit.