Biasing circuit for isolation region in integrated power circuit

An integrated circuit including a vertical power component having a terminal formed by a chip substrate (1) of a first conductivity type, a control circuitry thereof, the control circuitry isolated from the substrate (1) by means of an isolation region (3) of a second conductivity type, and a protection structure against polarity inversion of a substrate potential (SUB). The protection structure comprises a first bipolar transistor (Q33) with an emitter connected to said isolation region and a collector connected to a reference potential input (12) of the integrated circuit, a bias circuit (Q11,R11,R22,R33,R44) for biasing the first bipolar transistor (Q33) in a reverse saturated mode when the substrate potential is higher than the reference potential, and a second bipolar transistor (Q22) with an emitter connected to the substrate and a base coupled to the isolation region for coupling the isolation region to the substrate through a high-impedance when the substrate potential is lower than the reference potential.