An integrated circuit device having a planar interlevel dielectric layer

An integrated circuit includes a conductive layer adjacent a semiconductor substrate (30). The conductive layer includes conductive lines (32) having gaps (40) therebetween. A fluoro-silicate glass (FSG) layer (36) that is over the patterned conductive layer fills the gaps between conductive lines (...

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Bibliographische Detailangaben
Hauptverfasser:	MAURY, ALVARO, ABDELGADIR, MAHJOUB ALI
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRIC ELEMENTS CHEMICAL SURFACE TREATMENT CHEMISTRY COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING MATERIAL WITH METALLIC MATERIAL COATING METALLIC MATERIAL DIFFUSION TREATMENT OF METALLIC MATERIAL ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL METALLURGY SEMICONDUCTOR DEVICES SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION
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Beschreibung
Zusammenfassung:	An integrated circuit includes a conductive layer adjacent a semiconductor substrate (30). The conductive layer includes conductive lines (32) having gaps (40) therebetween. A fluoro-silicate glass (FSG) layer (36) that is over the patterned conductive layer fills the gaps between conductive lines (32). Also, an undoped oxide layer (38) is on the FSG layer (36). Peaks (42) of the FSG layer which overlie the conductive metal lines have been reduced by CMP. Thus, a subsequent conductive layer is substantially protected from exposure to fluorine from the FSG layer.