Multi-stage data anticipation driver and method for an integrated circuit device

A multi-stage data anticipation driver for an integrated circuit device includes a multi-stage data driver in which a first stage (124,134) initially turns "on" inducing a relatively small rate of change of current (di/dt) at an output data node. After a short predetermined delay, a second subsequent stage (132,142) turns on which provides another small di/dt. By step-wise controlling the rate of change in di/dt in this fashion, noise on the power supply lines is greatly limited. Following another short, predetermined delay, the second stage (132,142) turns "off" leaving only the first stage driver (124,134) driving the output data node and then only the first stage driver need turn "off" when opposite state data is read. Switching time for the first stage driver (124,134) can be made rapid by the reduction in device size allowed by the multi-stage configuration which also serves to limit the maximum possible crowbar current flow between the power supply lines.