Method for forming a dram capacitor and capacitor made thereby

An integrated DRAM cell comprises a DRAM capacitor and a transistor. The capacitor (17,18,20) of the cell is formed in a first well (16) in a dielectric layer (13) overlying the cell transistor. The top electrode (20) of the capacitor also serves as a barrier layer between an underlying plug (15) in a second well (19) in the dielectric layer. A method of forming the cell comprises the step of using a single mask for formation of the layer which acts as both the top electrode of the capacitor and the barrier layer of the second well.