Method of controlling cache memory in multiprocessor system and the multiprocessor system

Cache control protocols can be switched during running without changing an architecture for a segment descriptor or page descriptor for indicating an attribute of an area to be accessed. A plurality of processors each including a cache memory constitute a multiprocessor system which shares a main memory via a system bus. Each processor has module detecting means for detecting execution of a module which accesses a shared memory area on the main memory, by comparing the virtual space number and the instruction segment number concerning the accessing module with those numbers concerning the software modules preset which may access the shared memory area. Memory access executed in a module detected by the module detecting means is controlled in a cache control protocol of a store-through scheme which updates a main memory simultaneously with update of a cache memory. Memory access executed in other modules is controlled in a cache control protocol of a store-in scheme which does not update a main memory at update of a cache memory.