Cache miss benchmarking

A processor core (102) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A cache (814) located within a megacell on a single integrated circuit (800) is provided to reduce instruction access time. Performance monitoring circuitry (852) is included within the megacell and monitors selected signals to collect benchmark events. The performance monitoring circuitry can be interrogated via a JTAG interface (850). A cache miss signal (816) is provided by the cache to the performance monitoring circuitry in order to determine the performance of the internal cache. Windowing circuitry (824) within the megacell allows benchmark events to be collected during selected windows of execution.