Multichip-module fabrication process

A circuit design is logically partitioned into a plurality of blocks. As a first hierarchial assembly level, the blocks are fabricated as individual submodules (20, 21) each including at least one electronic component (22, 24) with component connection pads (26, 28, 30, 32) on a top surface (34, 36), and a first interconnect structure (50) including at least one interconnect layer (56, 58) bonded to the top surfaces (34, 36), and interconnecting selected ones of the component connection pads (26, 28, 30, 32). Submodule connection pads (76) are provided on upper surfaces (78) of the submodules (20, 21). As a second hierarchial assembly level, a second interconnect structure (186) is bonded to the upper surfaces (78) and interconnects selected ones of the submodule connection pads (76).