Method and system for buffering instructions in a processor
According to one embodiment of the invention, a method of buffering instructions in a processor (12) having a pipeline having a decode stage includes detecting stalling of the decode stage, reissuing a previous fetch for an instruction in a memory until the decode stage is no longer stalled, and wri...
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | According to one embodiment of the invention, a method of buffering instructions in a processor (12) having a pipeline having a decode stage includes detecting stalling of the decode stage, reissuing a previous fetch for an instruction in a memory until the decode stage is no longer stalled, and writing the fetch instruction into an instruction buffer after the decode stage is no longer stalled. |
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