DRAM trench capacitor production method

According to the present invention there is provided an improved process for manufacturing DRAM cells comprising the steps of depositing a first layer of silicon into a french, depositing approximately 50 nm of a second layer of silicon and allowing an interfacial oxide layer to grow on the trench side-wall and on top of the first layer of silicon, applying an anisotropic silicon etch to expose the oxide on top of the trench while protecting the oxide layer on the side of the trench, and applying a wet-chemical etch to remove the exposed oxide layer. This process then continues as standard. The improved method reduces the contact resistance of the buried strap and thus improves the production yield for low temperature performance cells.