SEMICONDUCTOR DEVICE COMPRISING A HALF-BRIDGE CIRCUIT

The invention relates to a half-bridge circuit comprising two series-connected n-channel DMOS transistors, in which the source of the one transistor, the low-side transistor T1, is connected to a low-voltage terminal Vss, and the drain of the other transistor, the high-side transistor T2, is connected to a high-voltage terminal Vdd. The drain of the low-side transistor and the source of the high-side transistor are connected to the output terminal (4). The circuit is arranged in a semiconductor body having an n-type or p-type epitaxial layer (11) which is applied to a p-type substrate (10). In the epitaxial layer, two n-type regions are defined for the transistors, each of said regions forming a drift region of one of the transistors and being surrounded by a cup-shaped n-type zone in the semiconductor body. Within the n-type cup-shaped zone (12) of the low-side transistor T1, there is provided a p-type cup-shaped zone which isolates the drift region (15) of T1 from the cup-shaped zone (12) and which is connected, along with the cup-shaped zone (12), the backgate region (17) and the source (19) of T1, to Vss. In the high-side transistor, the n-type cup-shaped region (13) is connected, together with the drain, to Vdd. As in the case of the low-side transistor, the n-type cup-shaped zone is at a fixed voltage, it is precluded that electrons are injected by this zone into the substrate, and, consequently, also the risk of latch-up and disturbances in the rest of the circuit is precluded. It is also precluded that, at a higher resistivity of the substrate, voltage jumps occur in the substrate, which could also give rise to latch-up and disturbances. In addition, at least the low-side transistor can be constructed in such a manner that the RESURF condition is met, thus enabling the device to be used also at a high voltage.