Method for planarising the device topography on solid state imagers

An improved and simplified process for reducing the topography within a solid state imager by using a single coat, expose, and development sequence to produce a transparent layer that fills in the topographic features surrounding the photoactive area while also planarizing the photoactive area. The topography within an imaging device is reduced by application of a transparent patternable layer to a semiconductor substrate having a plurality of image sensors with topographic features including structures in the photoactive area and in the periphery around the photoactive area including metal wiring and bond pads followed by a patterning step of this first layer by patternwise activating exposure. The result after pattern development is that the transparent layer is removed only from those areas with topographic features that are substantially higher than the surrounding area and the bond pads. This layer also remains over the photoactive area to serve as a planarizing layer. At this point, a CFA and/or lenslets may be formed over the photoactive area and the uniformity of the coating will be substantially improved over the uniformity obtained using planarizing layers within the prior art.