Processor having internal control instructions

The present invention relates to a processor provided with a set of instructions formed, in general, of an operation section (S1) and an operand section (S2); for at least one (CNTR) of the instructions, the operand section (S2) represents operation control signals (CO) of the processor. In this way, an extension of the set of instructions can be simulated for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit (UC) should be capable of coupling its outputs (CO) to its inputs (II) upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.