CURRENT MEMORY AND CIRCUIT ARRANGEMENT COMPRISING CURRENT MEMORIES

A current memory cell comprises a fine MOS memory transistor (T1) and a coarse MOS memory transistor (T2) connected in series between two power supply rails. Such current memory cells are preferably designed so that the sum of the voltage drops across the coarse and fine memory transistors when diode connected is equal to the supply voltage. In order to achieve this while leaving flexibility in choosing the transistor saturation voltages an auxiliary power rail (Vdda) is generated using as a reference the voltage drops across two diode connected transistors (T6, T7) which conduct a current equal to the bias current in the current memory cell (3).