A method and apparatus for reducing the bias current in a reference voltage circuit

A method and apparatus for reducing the bias current in a reference voltage circuit

A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: WEINFURTNER, OLIVER
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
CONTROLLING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
REGULATING
SEMICONDUCTOR DEVICES
STATIC STORES
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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Beschreibung
Zusammenfassung:A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to the Vref-node at predetermined time intervals during a power down mode, in order to ensure leakage compensation. When the power down mode exceeds a predetermined time, the reference voltage circuit is disabled to further reduce the current consumption.