Planar DMOS transistor fabricated by a three mask process

A planar DMOS power transistor (MOSFET) fabricated using only three masking steps, resulting in a significant reduction in fabrication cost. The resulting device is in terms of operations similar to prior art devices formed using more masking steps. Both the source and body regions are formed by implantations through the identical openings in the polysilicon/gate oxide layers into the substrate. After a subsequent glass layer is deposited and masked to expose openings, body contact regions are implanted into the source regions by overdoping the source region dopant concentration. The third masking step is the metal mask which also forms a termination structure.