Start code detecting apparatus for video data stream

An apparatus for providing a time delay to a group of compressed pictures, the pictures corresponding to a video compression/decompression standard, characterized by :words of data containing compressed pictures ;a counter circuit adapted to count said words of data ;a microprocessor in communicatio...

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Bibliographische Detailangaben
Hauptverfasser: FINCH, HELEN ROSEMARY, SOTHERAN, MARTIN WILLIAM, BOYD, KEVIN JAMES, ROBBINS, WILLIAM PHILIP, WISE, ADRIAN PHILIP
Format: Patent
Sprache:eng ; fre ; ger
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Beschreibung
Zusammenfassung:An apparatus for providing a time delay to a group of compressed pictures, the pictures corresponding to a video compression/decompression standard, characterized by :words of data containing compressed pictures ;a counter circuit adapted to count said words of data ;a microprocessor in communication with said counter circuit and adapted to receive start-up information consistent with the standard of video decompression ;said microprocessor communicating said start-up information to said counter circuit ;a token formatter, accepting from the data stream first type tokens having a first predetermined width, and at least one of the following formats :Format A - having a bit E, at least one bit L, and at least one bit xFormat B - having a bit E, at least one bit R, and at least one bit LFormat C - having a bit E, at least one bit 0, and at least one bit L,where E=extension bit ; F=specifics format ; R=run bit ; L=length bit or non-data token ; x="don't care" bit,said token formatter operating on said tokens by :splitting format A tokens into a format 0a token having a bit E, at least one bit L, and no bits x ;splitting format B tokens into a format 1 token having a bit F, at least one bit R, at least one bit 0 and a said format 0a data token ;splitting format C tokens into a format 0 token having a bit F, at least one bit L, and no bits 0 ; andpacking format 0, format 0a and format 1 tokens into a buffer, said buffer having a second predetermined width ; andan inverse modeller circuit for accepting said words of data from said buffer and capable of delaying said words of data ;a control circuit intermediate and in communication with said counter circuit and said inverse modeller circuit ;said counter circuit comparing said start-up information with said counted words of data and signaling said control circuit ; and said control circuit queueing said signals in correspondence to said words of data that have met a start-up criterion and controlling said inverse modeller delay feature.