Flip chip packaging of memory chips
The specification describes an interconnect strategy for memory chip packages to reduce or eliminate alpha particle contamination from the use of high lead solder interconnections in the vicinity of semiconductor memory cells. In the primary embodiment a high tin solder is recommended. A multi-layer...
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creator | TAI, KING LIEN DEGANI, YINON DUDDERAR, THOMAS DIXON |
description | The specification describes an interconnect strategy for memory chip packages to reduce or eliminate alpha particle contamination from the use of high lead solder interconnections in the vicinity of semiconductor memory cells. In the primary embodiment a high tin solder is recommended. A multi-layer under bump metallization is described that is compatible with high tin solders and flip-chip solder bump technology. |
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In the primary embodiment a high tin solder is recommended. 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In the primary embodiment a high tin solder is recommended. A multi-layer under bump metallization is described that is compatible with high tin solders and flip-chip solder bump technology.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFB2y8ksUEjOABIFicnZiemZeekK-WkKuam5-UWVYIliHgbWtMSc4lReKM3NoODmGuLsoZtakB-fWgzUl5qXWhLvGmBgYWFoZm7maGxMhBIAbacltw</recordid><startdate>20051109</startdate><enddate>20051109</enddate><creator>TAI, KING LIEN</creator><creator>DEGANI, YINON</creator><creator>DUDDERAR, THOMAS DIXON</creator><scope>EVB</scope></search><sort><creationdate>20051109</creationdate><title>Flip chip packaging of memory chips</title><author>TAI, KING LIEN ; DEGANI, YINON ; DUDDERAR, THOMAS DIXON</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0881676A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2005</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>TAI, KING LIEN</creatorcontrib><creatorcontrib>DEGANI, YINON</creatorcontrib><creatorcontrib>DUDDERAR, THOMAS DIXON</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TAI, KING LIEN</au><au>DEGANI, YINON</au><au>DUDDERAR, THOMAS DIXON</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Flip chip packaging of memory chips</title><date>2005-11-09</date><risdate>2005</risdate><abstract>The specification describes an interconnect strategy for memory chip packages to reduce or eliminate alpha particle contamination from the use of high lead solder interconnections in the vicinity of semiconductor memory cells. In the primary embodiment a high tin solder is recommended. A multi-layer under bump metallization is described that is compatible with high tin solders and flip-chip solder bump technology.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Flip chip packaging of memory chips |
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