GaAs vertical fet

A method of fabricating a GaAs vertical FET (20) including implanting a termination species to form termination areas (27) in the surface (24) of a substrate (21) defining transistor boundaries. A gate contact species (28) and a source species (30) are implanted in the surface (24) of the substrate (21) within the boundaries defined by the termination areas (27). Trenches (32) are formed in the surface (24) of the substrate (21) on opposing sides of the source species (30). Carbon and a lattice damaging species are co-implanted to form gate regions (33) in the trenches (32). All of the species and carbon are activated by annealing. Source and gate contacts (12, 11) are formed in communication with the source and gate species (30, 33), and a drain contact (45) is formed on the rear surface (25) of the substrate (21).