Circuit for recovery of a common clock treating multiple data signals

Each input data signal ÄD1Ü together with separate clock signal are stored ÄES1Ü and are then read by applying a separate read clock signal ÄTLÜ that are frequency and phase related. Outputs are applied to a phase discriminator ÄPD 1Ü that is an RS latch. The outputs of all such stages are fed to a...

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Bibliographische Detailangaben
1. Verfasser:	RUTHEMANN, KLAUS
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY MULTIPLEX COMMUNICATION TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	Each input data signal ÄD1Ü together with separate clock signal are stored ÄES1Ü and are then read by applying a separate read clock signal ÄTLÜ that are frequency and phase related. Outputs are applied to a phase discriminator ÄPD 1Ü that is an RS latch. The outputs of all such stages are fed to a multiplexer MUX and the output ÄPSÜ is processed to provide the common clock signal.