Testable sequential counter

An integrated circuit counter is capable of implementing a relatively high count while being testable using a relatively low number of clock cycles. A linear-feedback shift register (LFSR101) having n bit positions (Q0, Q19) is used as the counter. The feedback path of the shift register includes an exclusive OR (XOR) gate (104) that couples selected bits (Q0..Q3) back to the input (D19) of the register, in order to implement a 2n -1 counter. Combinatorial logic circuitry (106) is included to test the counter in significantly less than 2n -1 clock cycles. This allows for implementing a testable "watchdog timer" that may be used to detect software runaway conditions in microprocessor systems, among other uses.