Addressing means and method

Addressing means and method

An electronic system (10') has an address generator (40) for generating a sequence of addresses (80-95, 80'-94'), each address (80-95, 80'-94'), having a first portion address (98) and a second portion address (97) and a peripheral (30') having therein locations (770, 7...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SHTAYER, RONEN, NEUSTADTER, MARC, NATAN, RAMI
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:An electronic system (10') has an address generator (40) for generating a sequence of addresses (80-95, 80'-94'), each address (80-95, 80'-94'), having a first portion address (98) and a second portion address (97) and a peripheral (30') having therein locations (770, 770') able to store data wherein each location (770, 770') corresponds to a second portion address (98). The peripheral (30') has therein an address decoder (70) coupled to the address generator (40) for accessing the same second portion address (98) for different values of the first portion address (97).