Delta-sigma analog-to-digital converter including charge coupled devices

A delta sigma modulator having reduced quiescent power consumption as compared to known delta sigma modulators utilizes no operational amplifiers and includes, in one embodiment, an input CCD (12) and a summing CCD (14) coupled to the output of the input CCD. A readout (16) is connected to receive output signals from the summing CCD. Both an integration/recirculation input CCD (18) and a comparator (20) are provided to receive output signals from the readout. The integration/recirculation input CCD (18) feeds back a charge to the summing CCD (14), and the output of the comparator (20) is connected to a fill and spill reference CCD (22), which also feeds back a charge to the summing CCD. The comparator output signal is an oversampled digitized version of the analog signal sampled by the input CCD. The comparator output signal is supplied to a low pass digital filter, and a decimator is connected to the output of the digital filter.