Address transition detection circuit

An address transition detection circuit (30) having a number of cells (1) supplied with respective address signals and output connected in a wired NOR configuration to generate a pulse signal (WN) on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal (ATDO) having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage (80) for generating an end-of-transition signal (ATDY) with a predetermined delay following reception of the pulse signal; and an output stage (35, 70) connected to the cells (1) and to the monostable stage (80), which generates the first switching edge of the address transition signal (ATDO) on receiving the pulse signal (WN), and the second switching edge on receiving the end-of-transition signal. The monostable stage (80) presents a compensating structure (40, 42, 44) for maintaining the delay in the switching of the end-of-transition signal (ATDY) stable alongside variations in temperature and supply voltage.