Two-pin distributed ethernet bus architecture

A two-pin bus architecture with a distributed arbitration scheme allowing a number of half-repeaters (12) or other network components to share the same bus (14). The two-pin bus architecture comprises an intermodule bus having only two conductors, and at least two network components, each having a t...

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Hauptverfasser:	SALETT, RON, FITE, DAVID, B. JR, FITE, ELAINE H
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator	SALETT, RON FITE, DAVID, B. JR FITE, ELAINE H
description	A two-pin bus architecture with a distributed arbitration scheme allowing a number of half-repeaters (12) or other network components to share the same bus (14). The two-pin bus architecture comprises an intermodule bus having only two conductors, and at least two network components, each having a two-pin bus interface unit (20) connecting the network components to the bus. The two-pin interface units together provide a distributed arbitration scheme, for controlling access to the bus when more than one network component is seeking access at approximately the same time. The architecture provides for the transfer of network data from one component or module to another, and for the transfer of state information from one network component to another to facilitate cooperation of multiple network components connected to the bus.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP0785650A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP0785650A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP0785650A13</originalsourceid><addsrcrecordid>eNrjZNANKc_XLcjMU0jJLC4pykwqLUlNUUgtyUgtykstUUgqLVZILErOyCxJTS4pLUrlYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyalAbfGuAQbmFqZmpgaOhsZEKAEAn4YqNw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Two-pin distributed ethernet bus architecture</title><source>esp@cenet</source><creator>SALETT, RON ; FITE, DAVID, B. JR ; FITE, ELAINE H</creator><creatorcontrib>SALETT, RON ; FITE, DAVID, B. JR ; FITE, ELAINE H</creatorcontrib><description>A two-pin bus architecture with a distributed arbitration scheme allowing a number of half-repeaters (12) or other network components to share the same bus (14). The two-pin bus architecture comprises an intermodule bus having only two conductors, and at least two network components, each having a two-pin bus interface unit (20) connecting the network components to the bus. The two-pin interface units together provide a distributed arbitration scheme, for controlling access to the bus when more than one network component is seeking access at approximately the same time. The architecture provides for the transfer of network data from one component or module to another, and for the transfer of state information from one network component to another to facilitate cooperation of multiple network components connected to the bus.</description><edition>6</edition><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1997</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970723&DB=EPODOC&CC=EP&NR=0785650A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970723&DB=EPODOC&CC=EP&NR=0785650A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SALETT, RON</creatorcontrib><creatorcontrib>FITE, DAVID, B. JR</creatorcontrib><creatorcontrib>FITE, ELAINE H</creatorcontrib><title>Two-pin distributed ethernet bus architecture</title><description>A two-pin bus architecture with a distributed arbitration scheme allowing a number of half-repeaters (12) or other network components to share the same bus (14). The two-pin bus architecture comprises an intermodule bus having only two conductors, and at least two network components, each having a two-pin bus interface unit (20) connecting the network components to the bus. The two-pin interface units together provide a distributed arbitration scheme, for controlling access to the bus when more than one network component is seeking access at approximately the same time. The architecture provides for the transfer of network data from one component or module to another, and for the transfer of state information from one network component to another to facilitate cooperation of multiple network components connected to the bus.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1997</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNANKc_XLcjMU0jJLC4pykwqLUlNUUgtyUgtykstUUgqLVZILErOyCxJTS4pLUrlYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyalAbfGuAQbmFqZmpgaOhsZEKAEAn4YqNw</recordid><startdate>19970723</startdate><enddate>19970723</enddate><creator>SALETT, RON</creator><creator>FITE, DAVID, B. JR</creator><creator>FITE, ELAINE H</creator><scope>EVB</scope></search><sort><creationdate>19970723</creationdate><title>Two-pin distributed ethernet bus architecture</title><author>SALETT, RON ; FITE, DAVID, B. JR ; FITE, ELAINE H</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0785650A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>1997</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>SALETT, RON</creatorcontrib><creatorcontrib>FITE, DAVID, B. JR</creatorcontrib><creatorcontrib>FITE, ELAINE H</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SALETT, RON</au><au>FITE, DAVID, B. JR</au><au>FITE, ELAINE H</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Two-pin distributed ethernet bus architecture</title><date>1997-07-23</date><risdate>1997</risdate><abstract>A two-pin bus architecture with a distributed arbitration scheme allowing a number of half-repeaters (12) or other network components to share the same bus (14). The two-pin bus architecture comprises an intermodule bus having only two conductors, and at least two network components, each having a two-pin bus interface unit (20) connecting the network components to the bus. The two-pin interface units together provide a distributed arbitration scheme, for controlling access to the bus when more than one network component is seeking access at approximately the same time. The architecture provides for the transfer of network data from one component or module to another, and for the transfer of state information from one network component to another to facilitate cooperation of multiple network components connected to the bus.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
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language	eng ; fre ; ger
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title	Two-pin distributed ethernet bus architecture
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