Interface architecture for connection to a peripheral component interconnect bus

A data processing system (10) includes a first bus (22) which couples a processor (12) and other components and is configured to operate in accord with a standard protocol. Plural functional modules (30-52), each performing a function required by the data processing system (10) are coupled to a second bus (54). The second bus (54) includes dedicated read/write enable lines (74,76) for each functional module (30-52) and plural data lines (80) coupled in common to all functional modules (30-52). A bridge module (56,58,60,62) includes a controller (62) which is coupled between the first and second busses (22,54). The controller (62) is responsive to a read or write command received from the processor (12), to apply a logic signal to the read/write enable circuits (74,76) coupled to a functional module (30-52) designated by the received command. The functional module (30-52) responds by either providing the requested data onto the data lines (80) of the second bus (54) or receiving data from the second bus (54) into the functional module (30-52), as the case may be. The dedicated read/write enable lines (74,76) for each functional module (30-52) allow plural functional modules (30-52) to be attached to the second bus (22) and to be controlled, without requiring special configuration of command inputs from the first bus. Direct memory accesses are also enabled, both to and from the functional modules (30-52).