Buffer for integrated circuit memories

Buffer for integrated circuit memories

The circuit of this invention includes a current-compensated output buffer (OBC) that decreases the output switching rate as the conditions for transient noise increase to provide operation at maximum speed during worst-case speed conditions while suppressing noise during worst-case noise conditions...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: COFFMAN, TIM M, ROBINSON, DENNIS R, LIN, SUNG-WEI, TRUONG, PHAT C, SYZDEK, RONALD J, COOTS, TIMOTHY J
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
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Beschreibung
Zusammenfassung:The circuit of this invention includes a current-compensated output buffer (OBC) that decreases the output switching rate as the conditions for transient noise increase to provide operation at maximum speed during worst-case speed conditions while suppressing noise during worst-case noise conditions. Transistors (M35-M42) in the output pre-driver stages (15,16) are used to limit the output-stage (14) charge and discharge rate. These limiting pre-driver transistors (M35-M42) are controlled by a supply-voltage (VCC) and temperature compensating circuit (BGC). Compensating circuit (BGC) includes long channel transistors configured to increase a reference current (IREF) with temperature and to decrease that reference current (IREF) with increase in supply voltage (VCC), the compensating circuit (BGC) providing biasing currents (IREFN and IREFP) to output stage (14).