Planar PIN diode and method of manufacturing the same
A process for prodn. of a planar PIN diode with laterally arranged P, I and N regions involves (a) epitaxially growing a semiconductor layer sequence, including an I layer (5), on a semi-insulating semiconductor substrate; and (b) implanting the P and N contact regions (9, 10) in the I layer (5). Al...
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| creator | BRUGGER, HANS |
| description | A process for prodn. of a planar PIN diode with laterally arranged P, I and N regions involves (a) epitaxially growing a semiconductor layer sequence, including an I layer (5), on a semi-insulating semiconductor substrate; and (b) implanting the P and N contact regions (9, 10) in the I layer (5). Also claimed is a planar PIN diode with laterally arranged P, I and N regions, the diode having a semi-insulating GaAs substrate bearing a semiconductor layer sequence comprising (i) a 10-200 nm. thick undoped buffer layer (2) of GaAs and an AlGaAs/GaAs superlattice; (ii) a 10-100 nm. thick GaAs layer (3) with 1% excess of As; (iii) a 5-20 nm. thick diffusion barrier layer (4) of AlAs, AlGaAs, GaInP or an AlAs/AlGaAs/GaInP superlattice structure; (iv) a 0.4-0.8 microns thick GaAs current-passing I layer (5) forming the lateral diode; (v) a 2-10 nm. thick AlAs, AlGaAs or GaInP etch-stop layer (6); and (vi) a 10-50 nm. thick GaAs protective layer (7). |
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Also claimed is a planar PIN diode with laterally arranged P, I and N regions, the diode having a semi-insulating GaAs substrate bearing a semiconductor layer sequence comprising (i) a 10-200 nm. thick undoped buffer layer (2) of GaAs and an AlGaAs/GaAs superlattice; (ii) a 10-100 nm. thick GaAs layer (3) with 1% excess of As; (iii) a 5-20 nm. thick diffusion barrier layer (4) of AlAs, AlGaAs, GaInP or an AlAs/AlGaAs/GaInP superlattice structure; (iv) a 0.4-0.8 microns thick GaAs current-passing I layer (5) forming the lateral diode; (v) a 2-10 nm. thick AlAs, AlGaAs or GaInP etch-stop layer (6); and (vi) a 10-50 nm. thick GaAs protective layer (7).</description><edition>7</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20011024&DB=EPODOC&CC=EP&NR=0762500B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20011024&DB=EPODOC&CC=EP&NR=0762500B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BRUGGER, HANS</creatorcontrib><title>Planar PIN diode and method of manufacturing the same</title><description>A process for prodn. of a planar PIN diode with laterally arranged P, I and N regions involves (a) epitaxially growing a semiconductor layer sequence, including an I layer (5), on a semi-insulating semiconductor substrate; and (b) implanting the P and N contact regions (9, 10) in the I layer (5). Also claimed is a planar PIN diode with laterally arranged P, I and N regions, the diode having a semi-insulating GaAs substrate bearing a semiconductor layer sequence comprising (i) a 10-200 nm. thick undoped buffer layer (2) of GaAs and an AlGaAs/GaAs superlattice; (ii) a 10-100 nm. thick GaAs layer (3) with 1% excess of As; (iii) a 5-20 nm. thick diffusion barrier layer (4) of AlAs, AlGaAs, GaInP or an AlAs/AlGaAs/GaInP superlattice structure; (iv) a 0.4-0.8 microns thick GaAs current-passing I layer (5) forming the lateral diode; (v) a 2-10 nm. thick AlAs, AlGaAs or GaInP etch-stop layer (6); and (vi) a 10-50 nm. thick GaAs protective layer (7).</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDANyEnMSyxSCPD0U0jJzE9JVUjMS1HITS3JyE9RyE9TyE3MK01LTC4pLcrMS1coyUhVKE7MTeVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGuAQbmZkamBgZOhsZEKAEAocAr3A</recordid><startdate>20011024</startdate><enddate>20011024</enddate><creator>BRUGGER, HANS</creator><scope>EVB</scope></search><sort><creationdate>20011024</creationdate><title>Planar PIN diode and method of manufacturing the same</title><author>BRUGGER, HANS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0762500B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2001</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BRUGGER, HANS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BRUGGER, HANS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Planar PIN diode and method of manufacturing the same</title><date>2001-10-24</date><risdate>2001</risdate><abstract>A process for prodn. of a planar PIN diode with laterally arranged P, I and N regions involves (a) epitaxially growing a semiconductor layer sequence, including an I layer (5), on a semi-insulating semiconductor substrate; and (b) implanting the P and N contact regions (9, 10) in the I layer (5). Also claimed is a planar PIN diode with laterally arranged P, I and N regions, the diode having a semi-insulating GaAs substrate bearing a semiconductor layer sequence comprising (i) a 10-200 nm. thick undoped buffer layer (2) of GaAs and an AlGaAs/GaAs superlattice; (ii) a 10-100 nm. thick GaAs layer (3) with 1% excess of As; (iii) a 5-20 nm. thick diffusion barrier layer (4) of AlAs, AlGaAs, GaInP or an AlAs/AlGaAs/GaInP superlattice structure; (iv) a 0.4-0.8 microns thick GaAs current-passing I layer (5) forming the lateral diode; (v) a 2-10 nm. thick AlAs, AlGaAs or GaInP etch-stop layer (6); and (vi) a 10-50 nm. thick GaAs protective layer (7).</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Planar PIN diode and method of manufacturing the same |
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