Planar PIN diode and method of manufacturing the same

A process for prodn. of a planar PIN diode with laterally arranged P, I and N regions involves (a) epitaxially growing a semiconductor layer sequence, including an I layer (5), on a semi-insulating semiconductor substrate; and (b) implanting the P and N contact regions (9, 10) in the I layer (5). Also claimed is a planar PIN diode with laterally arranged P, I and N regions, the diode having a semi-insulating GaAs substrate bearing a semiconductor layer sequence comprising (i) a 10-200 nm. thick undoped buffer layer (2) of GaAs and an AlGaAs/GaAs superlattice; (ii) a 10-100 nm. thick GaAs layer (3) with 1% excess of As; (iii) a 5-20 nm. thick diffusion barrier layer (4) of AlAs, AlGaAs, GaInP or an AlAs/AlGaAs/GaInP superlattice structure; (iv) a 0.4-0.8 microns thick GaAs current-passing I layer (5) forming the lateral diode; (v) a 2-10 nm. thick AlAs, AlGaAs or GaInP etch-stop layer (6); and (vi) a 10-50 nm. thick GaAs protective layer (7).