Method and circuit for clock synchronisation of a digital coder and decoder

The method involves receiving a data frame including a data packet. The packet is decoded and written in a memory (23). The decoded data in the memory is read at a clock frequency of a decoder. Memory filling state is compared to a threshold, at a determined instant. Phase locking loop (18) of the d...

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Bibliographische Detailangaben
Hauptverfasser:	BASSI, THIERRY, RAMBAULT, CLAUDE
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY MULTIPLEX COMMUNICATION PICTORIAL COMMUNICATION, e.g. TELEVISION TRANSMISSION TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	The method involves receiving a data frame including a data packet. The packet is decoded and written in a memory (23). The decoded data in the memory is read at a clock frequency of a decoder. Memory filling state is compared to a threshold, at a determined instant. Phase locking loop (18) of the decoder is corrected according to the comparison result. An independent claim is also included for a device for receiving digital signals.