ARCHITECTURE AND METHODS FOR A HARDWARE DESCRIPTION LANGUAGE SOURCE LEVEL ANALYSIS AND DEBUGGING SYSTEM

ARCHITECTURE AND METHODS FOR A HARDWARE DESCRIPTION LANGUAGE SOURCE LEVEL ANALYSIS AND DEBUGGING SYSTEM

A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analys...

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Bibliographische Detailangaben
Hauptverfasser: ESTRADA, PAUL, SEAWRIGHT, ANDREW, GIRCZYC, EMIL, RAGHVENDRA, SRINIVAS, CHATTERJEE, TRINANJAN, LIN, JING, C, GREGORY, BRENT
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Zusammenfassung:A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.