Process for the manufacturing of integrated circuits comprising lateral low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells

A process for the manufacturing of an integrated circuit comprising lateral DMOS-technology power devices and non-volatile memory cells provides for: forming respective laterally displaced isolated semiconductor regions (R1,R2,R6), electrically insulated from each other and from a common semiconductor substrate (1), inside which the devices will be formed; forming conductive insulated gate regions (33,34,37) for the lateral DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions (R1,R2,R6); inside the isolated semiconductor regions (R1,R2) for the lateral DMOS-technology power devices, forming deep body regions (25,26) aligned with edges of the insulated gate regions (33,34), and channel regions (29,30) extending under the insulated gate regions (33,34). The deep body regions (25,26) are formed by means of a first implantation of a first dopant in a direction substantially orthogonal to a top surface of the integrated circuit, performed with an energy and with a dopant dose such that the concentration of the first dopant has a peak located at a prescribed distance from the surface of the isolated semiconductor regions (R1,R2). The channel regions (29,30) are formed by means of a second implantation of a second dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that said channel regions (29,30) are formed directly after the implantation of the second dopant without performing a thermal diffusion at a high temperature of the second dopant.