Information processing apparatus for prefetching data structure either from a main memory or its cache memory

To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit (105) incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory (1001) or a main memory (1) under the control of a cache request unit (101). A plurality of groups of data can be prefetched. When data designation is made, the processor (2) requests the cache memory (1001) to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit (105), wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor (2).