Method and system for the design verification of logic units and use in different environments

Disclosed are a method and a system concerning the verification for physical failures in digital circuits which accidently occurred within their fabrication process and in particular, the verification of logic units to be free of design errors. Prior art systems do only check physical failures in logic devices. Those test units use correct reference models which can exist as a physical reference model or a mathematical abstraction of such a unit. Verification is fulfilled by comparing the physical copies with the reference model. On the contrary, the invention provides a method and a system for the design verification of logic units (1) which is suitable to verify the design of logic units before chip production and which can be implemented with a much more less effort than known prior art systems. At least one test unit (5, 6, 7) is provided which is connected with a logic unit (1) via interface means (2, 3, 4), whereby the test units comprise a set of test operations (11, 12, 13) which are applied to the logic unit. In particular, the selection of test operations and the determination of their start times are executed randomly and independently of each other. In case of generating events, this new approach modifies independently two parameters in a random way: 1. The "sequence" of the test operations; and 2. the temporal relationship between these operations.