Linewidth metrology of integrated circuit structures

Illustratively, the present invention includes a method of integrated circuit manufacturing which includes forming a raised topological feature (31) upon a first substrate (40). A portion of the raised feature is removed, thereby exposing a cross sectional view of the raised feature with the substra...

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Bibliographische Detailangaben
Hauptverfasser:	DARE, RICHARD J, BINDELL, JEFFREY B, PLEW, LARRY E, SCHROPE, DENNIS E, STEVIE, FRED A
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	APPLICATIONS OF SCANNING-PROBE TECHNIQUES, e.g. SCANNING PROBEMICROSCOPY [SPM] BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MEASURING PHYSICS SCANNING-PROBE TECHNIQUES OR APPARATUS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS TESTING
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Beschreibung
Zusammenfassung:	Illustratively, the present invention includes a method of integrated circuit manufacturing which includes forming a raised topological feature (31) upon a first substrate (40). A portion of the raised feature is removed, thereby exposing a cross sectional view of the raised feature with the substrate remaining substantially undamaged. The cross sectional view has a critical dimension. The critical dimension of the cross sectional view is measured using a first measuring instrument. Then the critical dimension is measured using a second measuring instrument. The measurements of the first and second measuring instruments are correlated. Then, using the second measuring instrument, raised features on a plurality of second substrates are measured.