PROCESSOR SYSTEM AND DEBUG MODE ACCOMPLISHMENT METHOD

A processor system switched between a normal operation mode without normal floating-point exception and a debug mode with normal floating-point exception. This processor system includes means for dispatching integer and floating-point commands, an integer unit equipped with a multi-stage integer pip...

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Bibliographische Detailangaben
Hauptverfasser: BRATT, JOSEPH, P, NOFAL, MONICA, R, JOSHI, CHANDRA, S, SCANLON, JOSEPH, T, RODMAN, PAUL, TANG, MAN, KIT, HUFFMAN, WILLIAM, A, BRENNAN, JOHN, HSU, PETER, YAN-TEK
Format: Patent
Sprache:eng ; fre ; ger
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