Analog-to-digital conversion device for low frequency low amplitude differential signals

An analog-to-digital conversion device (ADD) adapted to convert a differential input signal having a very low amplitude and a low frequency into a digital word. The device includes the cascade connection of a chopper (CHP), a differential amplifier (AMP), a dechopper (DCH) and an analog-to-digital converter (ADC). The differential amplifier includes at least one stage (AS) arranged as a high-pass filter/amplifier whereby the device does not requires any additional anti-aliasing filter or other filter to eliminated unwanted signals such as DC offset signals. Furthermore, the chopper and the dechopper operate at a clock frequency which is equal to or a multiple of the clock frequency of the analog-to-digital converter. The high-pass filtering is obtained by means of an integrator circuit (V1, C1, R13; V2, C2, R23) connected in feedback over each amplifier section (A1, R11, R12; A2, R21, R22) of the differential amplifier stage (AS). The output of an integrator circuit is coupled to an input of the associated amplifier section via a voltage divider (R14-R15; R24-R25) constituted by two resistors in series. The two voltage dividers of a differential pair of amplifier sections are interconnected at a common floating terminal (COM) in order to eliminate unwanted common mode signals.