A computer apparatus having a means to force sequential instruction execution

SA computer apparatus which detects a store or load operation into or from a shared memory page (809) by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store (815) into the shared memory page (809) is performed until all prior store operations (813) into the shared memory page (809) are complete. Also, load operations are ordered such that load operations from the shared memory page (809) are performed in program order. This ordering is achieved by maintaining a process bit (811) and a memory attribute bit (819) associated with a shared memory page (809). When both bits (811, 819) are true, all load or store operations referencing the shared memory page (809) are ordered.