Flash EEPROM and EPROM arrays

Flash EEPROM array and EPROM arrays are described. The EEPROM array has EEPROM areas with arrays of EEPROM transistors, at least one control area per EEPROM area and columns of a first polysilicon layer traversing the EEPROM and control areas. The columns are divided into even and odd columns. Each control area is divided into upper, middle and lower areas and each control area includes the following: a) within the middle area, cross-lines of the first polysilicon extending from each even to the next odd column; b) four rows of a second polysilicon layer, laid down after the columns and cross-lines of the first polysilicon layer within the control areas are removed; and c) isolating oxide elements laid down prior to the first polysilicon layer and self-aligned to it before it is removed. The isolating oxide elements are located under every odd column in the upper area, under each column in the middle area, under each odd column in one row of the lower area and under each even column in the other row of the lower area. Bit line select and erase select rows are in the upper and middle areas, respectively, and two column select rows are in the lower area. Erase select transistors are formed at the intersections of the removed cross-lines with the erase select row of second polysilicon, bit line select transistors are formed at the intersections of removed even columns with the bit line select row of second polysilicon, and column select transistors are formed at intersections of the column select rows of second polysilicon with the removed columns wherever no isolating oxide elements exist. The EPROM array has a similar structure but does not include the erase select transistors. The select transistors are n-channel transistors each formed of a) a channel, b) two diffusion bit lines bordering the channel and aligned to a first, subsequently removed, polysilicon layer and c) a second polysilicon layer extending between and over the two diffusion bit lines. The EPROM array having self-aligned thick oxide isolation units and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin ox