Circuitry and method for caching information
A method and circuitry are provided for caching information. Multiple first memory locations (108, 204) store information. The first memory locations (108, 204) are of multiple classes, and each class includes multiple ones of the first memory locations (108, 204). Multiple second memory locations (...
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| Format: | Patent |
| Sprache: | eng ; fre ; ger |
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| Zusammenfassung: | A method and circuitry are provided for caching information. Multiple first memory locations (108, 204) store information. The first memory locations (108, 204) are of multiple classes, and each class includes multiple ones of the first memory locations (108, 204). Multiple second memory locations (102, 202) store information from the first memory locations. Multiple directory locations (104, 216) store information relating the first (108, 204) and second (102, 202) memory locations (108, 204). Each directory location (104, 216) is able to relate a second memory location (102, 202) to any of multiple first memory locations (108, 204) in more than one class. |
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