Single event upset hardening of commercial VLSI technology without circuit redesign

Single event upset hardening of commercial VLSI technology without circuit redesign

A fabrication method whereby any commercial integrated circuit design can be made SEU hardened simply by the fabrication process. No circuit redesign is required nor is circuit performance degraded. The novel method employs fully depleted accumulated mode type transistors on a silicon-on-insulator s...

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Bibliographische Detailangaben
Hauptverfasser: BRADY, FREDERICK T, HADDAD, NADIM F, WANG, LI KONG, EDENFELD, ARTHUR R, SPENCER, OLIVER, SELISKAR, JOHN J
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A fabrication method whereby any commercial integrated circuit design can be made SEU hardened simply by the fabrication process. No circuit redesign is required nor is circuit performance degraded. The novel method employs fully depleted accumulated mode type transistors on a silicon-on-insulator substrate. Modified LDD fabrication techniques are employed.