Semiconductor integrated circuit device with test mode switching

A mode selector is disclosed, for causing a testing circuit (29) in an LSI to test an internal circuit (22) of the LSI. The mode selector includes an N channel MOS transistor (25) having a source, and a gate and drain which are connected to an input terminal (21) of the LSI, and a P channel MOS transistor (26) having a gate, a source connected to the source of the N channel MOS transistor and a drain for outputting a mode change signal to the testing circuit (29) based on a control voltage to be applied to the gate of the P channel MOS transistor (26). The mode selector further includes a voltage supplying circuit (24) for applying the control voltage to the gate of the P channel MOS transistor (26). The control voltage is so set as to turn the N channel MOS transistor and the P channel MOS transistor on, when a voltage higher than the normal operation voltage is applied to the input terminal (21).