Semiconductor memory device

A semiconductor memory device includes a memory cell array (2), an address part (3 - 6) for supplying address signals to the memory cell array, a read/write part (7 - 12) for reading data from the memory cell array and writing data into the memory cell array, and an internal clock signal generating circuit (62) for generating an internal clock signal from an external clock signal. The internal clock signal has a cycle with an active-level portion of constant duration independent of a frequency of the external clock signal and is output, as a timing signal, to predetermined structural parts of the address part and/or the read/write part.