Microprocessor circuit having two timing signals

A microprocessor circuit is provided that allows the internal microprocessor clock speed to vary depending upon a register that can be programmed by software. In addition, the drive strength of the internal clock generator may similarly be varied by software programming. The programmer or user of the microprocessor may change the internal clock speed such that the microprocessor operates at a first frequency or at a second frequency depending upon the performance requirements. A lower frequency of operation may be selected for low power consumption and low EMI, while a higher frequency of operation may be selected for computational intensive and high performance applications.