Error recovery mechanism for software visible registers in computer systems

A CPU is so structured as to include a CSVR which stores, the same contents as a software visible register (SVR) of one cycle earlier. Upon occurrence of an error in a calculation unit, an error flag is activated. At the same time, data at the time of error occurrence are written into the SVR. The activation of the error flag inhibits writing into the CSVR. In this case, the instruction which was being executed when the error occurred is restarted by restoring the contents of the CSVR into the SVR. On the other hand, if an error is detected in the CSVR, the instruction is restarted with the contents of the SVR restored to the SVR. Error processing is accomplished under the control of a diagnostic processor. By setting the mode flag appropriately, an instruction is given as to whether firmware for the generation of the timing of control shift to the diagnostic processor is to be gone through or not.